The present invention relates to memory devices, and more particularly, to a method and related apparatus for the calibration of memory devices.
Memory is an important element found in many types of electronic devices. With recent rapid technological improvements, an increased number of DRAMs are now supplied as a common memory type of electronic devices. There are several kinds of DRAMs currently available on the market. For example, a synchronous DRAM (also referred to as SDRAM) is a kind of DRAM that can be continuously written to and read from at high speeds in synchronism with the clock of the interface (the read/write process is also referred to as a burst transfer). A double data rate SDRAM (also referred to as DDR SDRAM) is a kind of DRAM that has a doubled burst transfer speed by executing the burst transfer of the SDRAM in synchronism with both the leading edge and the trailing edge of the clock signal. Since SDRAMs constitute an inexpensive and large-capacity memory source, their usage is becoming more commonly employed in electronic devices.
A mechanism can be provided for calibration during system initialization within a memory device. For example, according to JEDEC Standard No. 79-2B, the Off-Chip driver (OCD) impedance of a DDR2 SDRAM can be adjusted during system initialization. More specifically, by using Extended Mode Register Set (EMRS) commands, the OCD impedance adjustment process of the DDR2 SDRAM can be achieved during system initialization. FIG. 1 shows a flowchart of the OCD impedance adjustment process according to JEDEC Standard No. 79-2B.
According to JEDEC Standard No. 79-2B, the OCD impedance adjustment can be done using two EMRS modes: a drive mode and an adjust mode. In the drive mode, all outputs are driven by the DDR2 SDRAM. More specifically, in Drive(1) mode, all DQ, DQS (and RDQS) signals are driven high and all /DQS signals are driven low. In Drive(0) mode, all DQ, DQS (and RDQS) signals are driven low and all /DQS signals are driven high. In the adjust mode, the OCD impedance value is adjusted according to the driving result of the drive mode. FIG. 2 and FIG. 3 show function tables of the OCD drive mode and OCD adjust mode, respectively.
FIG. 4 shows a conventional memory system 400 comprising a memory controller 410 and a memory device 450, which is a DDR2 SDRAM in this example. According to JEDEC Standard No. 79-2B, the OCD impedance adjustment process is performed during system initialization. The goal of OCD impedance adjustment is that the pull-up and pull-down driving strengths of the output drivers 460 and 470 of the DDR2 SDRAM 450 are optimized. In the memory controller 410, the command generator 430 has the task of sending control commands (such as read, write, and EMRS commands) to the DDR2 SDRAM 450. Through the EMRS commands, the memory controller 410 can adjust the OCD impedance of the DDR2 SDRAM 450 so as to optimize the driving strengths of the output drivers 460 and 470. The OCD detector 420 is in charge of detecting the voltage levels of the signals outputted by the output drivers 460 and 470. If the voltage levels of the signals outputted by output drivers 460 and 470 are within required target range when the DDR2 SDRAM 450 is in drive mode, then the calibration process will be completed and the memory system 400 can undergo normal operation. If the voltage levels of the signals from output drivers 460 and 470 are not within the required target range, the command generator 430 will then send EMRS commands to the DDR2 SDRAM 450 in order to adjust the OCD impedance value and force the DDR2 SDRAM 450 into drive mode. The OCD detector 420 will then re-test the received voltage levels. The calibration process will continue until the voltage levels are adjusted to the required target range.
Memory systems of the related art only perform the calibration process during system initialization. For example, a memory system including a DDR2 SDRAM performs the OCD impedance calibration procedure only during system initialization. This will ensure that the pull-up and pull-down driving strengths of the output drivers of the DDR2 SDRAM are optimized only at the beginning of system operation. However, throughout system operations, the operating environment (including operating voltages and temperature) may change from time to time. This variation during system operation may cause the pull-up and pull-down driving strengths of the output drivers on the DDR2 SDRAM to fluctuate. After a long usage of the memory system, the device may become unstable due to inaccurate output driving strengths, potentially causing the memory system to crash. Therefore, there is a need to provide a new mechanism that ensures optimal operation for memory systems throughout system operation without sacrificing performance.